FX809 ffsk modem fig 1. FX809 ffsk modem brief description an intelligent, half-duplex, ffsk/msk modem which operates under c-bus control. in addition this modem provides software selectable checksum generation and error checking, in accordance with mpt1327. the FX809, using interrupt and status register procedures, performs the functions described below: in tx mode the FX809 will: 1. (a) accept from the host and transmit, 8-bit bytes of data as instructed (preamble, sync, address and data). (b) internally calculate and insert a 2 byte checksum based upon the preceeding 6 bytes of data, or (c) disable the internal checksum generator and continuously transmit the data supplied. 2. transmit 1 hang-bit and go to tx idle when all loaded data bytes have been transmitted. in rx mode the FX809 will: 1. detect and achieve bit synchronization within 16 bits. 2. (a) search and detect the user-programmed sync (or its opposite logic sense) word and achieve frame sychronization. data will then be output in 8-bit bytes via the rx data buffer. rx in serial clock command data checksum gen/check interrupt generator address select tx out recovered clock ffsk transmitter recovered clock 8-bit parallel bus ffsk receiver xtal/clock clock generator status register uncommitted amplifier amp in amp out reply data c-bus interface and control logic sync/sync detect tx data buffer rx data buffer data register 1 data register 2 C + rx sync detect byte counter rx data ready tx data ready tx idle v bias v bias v ss v dd interrupt enable rx sync detect address decoder rx free format control register rx sync detect rx sync detect xtal wake cs sync program low C high irq (b) use the received checksum to calculate the presence of any errors, setting the status register accordingly. 3. make the incoming data directly available, via the rx data buffer (rx freeformat), overriding synchronization requirements. the FX809 achieves rx input timing by recovering an rx clock from the incoming data stream. output tones are timed to the internally generated transmit clock. filter, register clocks and transmit ffsk tone frequencies are derived internally from the external xtal or clock pulse input. for compliance with the mpt 1327 signalling specification a 4.032mhz xtal or clock input will be required. note: all information contained in this data sheet is specified using a 4.032 mhz xtal, 1200 bps baud rate , mark and space frequencies 1200 hz and 1800 hz. the FX809 is a low-power 5-volt integrated circuit, incorporating powersave modes to further reduce power requirements. an uncommitted amplifier is provided on chip for general purpose applications within dbs 800. the FX809 is available in 24-pin cerdip dil and 24- pin/lead plastic smd packages. publication d/809/5 april 1998
pin numbe r function FX809 j/lg/ls 1 2 3 4 5 6 7 8 9 10 11 12 xtal: the output of the on-chip clock oscillato r . external components are required at this input when a xtal input is used. see figure 2, inse t . xtal/clock: the input to the on-chip clock oscillator inverte r . a xtal or externally derived clock should be connected here. see figure 2, inse t . interrupt request (irq) : the output of this pin indicates an interrupt condition to the m controlle r , by going to a logic 0. this is a wire-or able output, enabling the connection of up to 8 peripherals to 1 interrupt port on the m controlle r . this pin has a low-impedance pulldown to logic 0 when active and a high-impedance when inactive . the system irq line requires a 'pull-up' resistor to v dd . the conditions that cause interrupts are indicated in the status register and are shown below: tx idle rx data ready tx data ready rx sync detect rx sync detect interrupt outputs can be disabled by bit 3 of the control registe r . no internal connection. no internal connection. rx freeformat: used in the rx mode, this input, when a logic 0, allows received data to be read from the rx data bu f fer via the reply data line without having to acheive byte synchronization (sync/sync) first. data will continue to be available after this input goes to a logic 1 until either a sync or sync prime bit is set or the the modem set t o tx mode. when held at a logic 1 the modem operates normall y . this pin has an internal 1m w pullup resisto r . note: if this input is held at a logic 0 in th e tx mode, the rx data ready bit in the status register may occasionally be set, but not cause an interrupt. if this input is a logic 0 when going into the rx mode, an rx data ready interrupt may be generated immediatel y , in this case the first byte of rx data should be ignored. v bias : the internal circuitry bias line, held at v dd /2 this pin must be decoupled to v ss by capacitor c 3 , see figure 2. amp in: the inverting input to the on-chip uncommitted amplifier . amp out: the output of the on-chip uncommitted amplifie r . rx in: the 1200 baud, 1200hz/1800hz, received ffsk signal input . the input signal to this pin must be a.c. coupled via capacitor c 4 , see figure 2. no internal connection. v ss : negative supply (gnd).
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 10 -5 10 -2 10 -3 10 -4 signal to noise ratio (db) [bit-rate bandwidth] bit error rate (logarithmic scale) ideal coherent ffsk characteristic 2 x 10 -2 2 4 6 3 8 FX809 characteristic (linear scale ) fig.3 bit error rate vs signal-to-noise ratio v bias xtal/clock v dd 13 14 15 16 17 18 19 20 21 22 23 2 4 1 2 3 4 5 6 7 8 9 10 11 12 FX809j v ss v dd tx out see inset xtal v ss rx freeformat signal out rx in reply data serial clock cs command data address select wake 2 1 xtal/clock xtal v ss inset FX809j r 1 c 1 c 2 c 3 c 4 c 5 irq x 1 r 4 signal in c 7 r 2 c 6 r 3 external components modem performance component value r 1 = 1.0m w r 2 note 1 r 3 100k w r 4 22.0k w c 1 33.0pf c 2 33.0pf c 3 1.0 m f c 4 0.1 m f c 5 1.0 m f c 6 33.0pf c 7 note 1 x 1 4.032mhz tolerance: r = 10% c = 20% fig.2 external components note 1: r 2 , r 3 and c 7 form the gain components for the signal; r 3 should be chosen as required by the signal input level.
handling precautions the FX809 is a cmos lsi circuit which includes input protection. however precautions should be taken to prevent static discharges which may cause damage. cml does not assume any responsibility for the use of any circuitry described. no circuit patent licences are implied and cml reserves the right at any time without notice to change the said circuitry. ordering information FX809j 24-pin cerdip dil (j4) FX809lg 24-pin encapsulated bent and cropped (l1) FX809ls 24-lead plastic leaded chip carrier (l2) package outlines the FX809 is available in the package styles outlined below. mechanical package diagrams and specifications are detailed in section 10 of this document. pin 1 identification marking is shown on the relevant diagram and pins on all package styles number anti-clockwise when viewed from the top. not to scale max. body length 10.25mm max. body width 10.25mm FX809lg 24-pin quad plastic encapsulated bent and cropped (l1) FX809j 24-pin cerdip dil (j4) not to scale max. body length 10.40mm max. body width 10.40mm FX809ls 24-lead plastic leaded chip carrier (l2) not to scale max. body length 32.03mm max. body width 14.81mm
|
